As companies worldwide try to improve their green credentials, their vendors are expected to reduce system power consumption. That in turn is driving ASIC and FPGA designers to reduce device power.
As companies worldwide try to improve their green credentials, their vendors are expected to reduce system power consumption. That in turn is driving ASIC and FPGA designers to reduce device power. Portable devices are also leading the push to reduce power consumption as battery life is crucial. High power consumption is also a major cause of performance degradation, reliability deterioration and packaging / cooling costs which needs to be addressed at the IC design level. With the shrinking geometries, static power is growing really fast and dynamic power is growing as well. Solving power is a key challenge for EDA companies today. Unlike logic, power information is not consistent across all design stages; architects often use gut feel to estimate power and there is no set process for transferring this information to tools downstream. As a result, each tool requires different inputs and works from a different database.
Existing tools are struggling to solve the power challenge. At the architecture level, they are inaccurate as clock / interconnect information is not considered. RTL / Gate level tools are fairly accurate at the block level, but not at the chip level as full chip simulation is practically impossible. FPGA emulation is often a common practice, but no existing tools can measure power from the platform. At the physical design level, P&R tools are focused on timing and placement, and not power. Manual power planning thus must be performed after floor plan is complete. Manual planning often increases die size. In addition, a sub-optimal clock approach is chosen. FPGA vendor specific tools are reasonably accurate at the block level, but not at the chip level as full chip simulation is practically impossible. It is also impractical to measure board current for accuracy.
PowerFactor is a set of three point tools:
PowerFactor XP for automated power exploration during architecture phase.
PowerFactor EM for automated power evaluation using FPGA emulation board.
PowerFactor LO for automated power planning and optimization at layout stage.
Sanved�s patent pending power optimization algorithms will reduce device power by up to 15%. Designers using the PowerFactor tool will be able to estimate power accurately across all design stages (up to 90%), cut time to market and avoid chip redesign due to power reasons. In addition, congestion relief, easier routing, early closure of IR drop and EM analysis, and die size reduction can be achieved.