In integrated circuit design, physical design is a step in the standard design cycle which follows after the circuit design. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations
Physical design is a step in Integrated circuit design, the standard design cycle which follows after the circuit design. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components. This geometric representation is called integrated circuit layout. This step is usually split into several sub-steps, which include both design and verification and validation of the layout
Modern day Integrated Circuit (IC) design is split up into Front-end design using HDLs, Verification, and Back-end Design or Physical Design. The next step after Physical Design is the Manufacturing process or Fabrication Process that is done in the Wafer Fabrication Houses. Fab-houses fabricate designs onto silicon dies which are then packaged into ICs.
Each of the phases mentioned above has design flows associated with them. These design flows lay down the process and guide-lines/framework for that phase. Physical design flow uses the technology libraries that are provided by the fabrication houses. These technology files provide information regarding the type of silicon wafer used, the standard-cells used, the layout rules (like DRC in VLSI), etc.
IO Planning/Floor-Planning/Power Planning/P&R/Metal Fills
Flip Chip designs with Package Level Interactions and closure.
Partitioning and Hardening. DFT scan insertion and Timing closure in Functional/Test modes. The design-cycle of VLSI-chips consists of different consecutive steps from high-level synthesis (functional design) to production (packaging) . The physical design is the process of transforming a circuit description into the physical layout, which describes the position of cells and routes for the interconnections between them. Figure 1 shows a schematic representation of a layout. The main concern in the physical design of VLSI-chips is to find a layout with minimal area, further the total wirelength has to be minimized. For some critical nets there are hard limitations for the maximal wirelength.
First the circuit has to be partitioned to generate some (up to 50) macro cells. In the floorplanning phase the cells have to be placed on the layout surface. After placement the global routing has to be done. In this step the `loose' routes for the interconnections between the single modules (macro cells) are determined. In the detailed routing the exact routes for the interconnection wires in the channels between the macro cells have to be computed. The last step in the physical design is the compaction of the layout, where it is compressed in all dimensions so that the total area is reduced.